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features description/ordering information pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 1-of-4 bidirectional translating switches no glitch on power up i 2 c bus and smbus compatible supports hot insertion four active-low interrupt inputs low standby current active-low interrupt output operating power-supply voltage range of 2.3 v to 5.5 v active-low reset input 5.5-v tolerant inputs two address pins, allowing up to four devices on the i 2 c bus 0 to 400-khz clock frequency channel selection via i 2 c bus, in any latch-up performance exceeds 100 ma per combination jesd 78 power up with all switch channels esd protection exceeds jesd 22 deselected ? 2000-v human-body model (a114-a) low r on switches ? 200-v machine model (a115-a) allows voltage-level translation between ? 1000-v charged-device model (c101) 1.8-v, 2.5-v, 3.3-v, and 5-v buses the pca9545a is a quad bidirectional translating switch controlled via the i 2 c bus. the scl/sda upstream pair fans out to four downstream pairs, or channels. any individual scn/sdn channel or combination of channels can be selected, determined by the contents of the programmable control register. four interrupt inputs ( int3? int0), one for each of the downstream pairs, are provided. one interrupt ( int) output acts as an and of the four interrupt inputs. an active-low reset ( reset) input allows the pca9545a to recover from a situation in which one of the downstream i 2 c buses is stuck in a low state. pulling reset low resets the i 2 c state machine and causes all the channels to be deselected, as does the internal power-on reset function. the pass gates of the switches are constructed such that the v cc pin can be used to limit the maximum high voltage, which will be passed by the pca9545a. this allows the use of different bus voltages on each pair, so that 1.8-v, 2.5-v, or 3.3-v parts can communicate with 5-v parts, without any additional protection. external pullup resistors pull the bus up to the desired voltage level for each channel. all i/o pins are 5.5-v tolerant. please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. production data information is current as of publication date. copyright ? 2005?2006, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www .ti.com rgy package (top view) 2 a1 19 sda 3 reset 18 scl 4 int0 17 int 5 sd0 16 sc3 6 sc0 15 sd3 7 int1 14 int3 8 sd1 13 sc2 9 sc1 12 sd2 1 10 a0 gnd 20 11 int2 v cc 20 6 8 9 10 12 3 4 5 1514 13 12 11 int2 sd2 sd1sc1 gnd 19 reset int0 sd0sc0 int1 int sc3sd3 int3 sc2 rgw package (top view) 18 17 16 7 sd a scl a1a0 v cc dgv, dw, or pw package (top view) 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 a0 a1 reset int0 sd0sc0 int1 sd1sc1 gnd v cc sda scl int sc3sd3 int3 sc2sd2 int2
description/ordering information (continued) pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 ordering information t a package (1) orderable part number top-side marking qfn ? rgw reel of 3000 pca9545argwr pd545a qfn ? rgy reel of 1000 pca9545argyr pd545a tube of 25 pca9545adw pca9545a soic ? dw reel of 2000 pca9545adwr reel of 250 pca9545adwt pca9545a pca9545apw pd545a tube of 70 pca9545apwe4 ?40 c to 85 c pca9545apwr pd545a tssop ? pw reel of 2000 pca9545apwre4 pca9545apwt pd545a reel of 250 PCA9545APWTE4 reel of 2000 pca9545adgvr tvsop ? dgv pd545a reel of 250 pca9545adgvt vfbga ? gqn reel of 1000 pca9545agqnr pd545a vfbga ? zqn (pb-free) reel of 1000 pca9545azqnr pd545a (1) package drawings, standard packing quantities, thermal data, symbolization, and pcb design guidelines are available at www.ti.com/sc/package. terminal assignments 1 2 3 4 a a1 a0 v cc sda b int0 int reset scl c sc0 sd0 sd3 sc3 d sd1 sc2 int1 int3 e gnd sc1 int2 sd2 2 submit documentation feedback www .ti.com gqn or zqn p ackage (t op view) 1 2 3 4 ab c d e
pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 terminal functions no. name description dgv, dw, pw, gqn and rgw and rgy zqn 1 19 a2 a0 address input 0. connect directly to v cc or ground. 2 20 a1 a1 address input 1. connect directly to v cc or ground. active-low reset input. connect to v cc through a pullup 3 1 b3 reset resistor, if not used. active-low interrupt input 0. connect to v cc through a 4 2 b1 int0 pullup resistor. 5 3 c2 sd0 serial data 0. connect to v cc through a pullup resistor. 6 4 c1 sc0 serial clock 0. connect to v cc through a pullup resistor. active-low interrupt input 1. connect to v cc through a 7 5 d3 int1 pullup resistor. 8 6 d1 sd1 serial data 1. connect to v cc through a pullup resistor. 9 7 e2 sc1 serial clock 1. connect to v cc through a pullup resistor. 10 8 e1 gnd ground active-low interrupt input 2. connect to v cc through a 11 9 e3 int2 pullup resistor. 12 10 e4 sd2 serial data 2. connect to v cc through a pullup resistor. 13 11 d2 sc2 serial clock 2. connect to v cc through a pullup resistor. active-low interrupt input 3. connect to v cc through a 14 12 d4 int3 pullup resistor. 15 13 c3 sd3 serial data 3. connect to v cc through a pullup resistor. 16 14 c4 sc3 serial clock 3. connect to v cc through a pullup resistor. active-low interrupt output. connect to v cc through a pullup 17 15 b2 int resistor. 18 16 b4 scl serial clock line. connect to v cc through a pullup resistor. 19 17 a4 sda serial data line. connect to v cc through a pullup resistor. 20 18 a3 v cc supply power 3 submit documentation feedback www .ti.com
pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 block diagram 4 submit documentation feedback www .ti.com switch control logic i 2 c bus control interrupt logic input filter power-on reset pca9545a sc0 a1 a0int int0 sda scl gnd sd3 sd2 sd1 sd0 sc3 sc2 sc1 9 1316 58 1215 6 1020 3 19 18 4 17 2 1 7 11 14 int1 int2 int3 pin numbers shown are for dgv , dw , pw , and rgy packages. output filter v cc reset
device address control register control register definition pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 following a start condition, the bus master must output the address of the slave it is accessing. the address of the pca9545a is shown in figure 1 . to conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. figure 1. pca9545a address the last bit of the slave address defines the operation to be performed. when set to a logic 1, a read is selected, while a logic 0 selects a write operation. following the successful acknowledgment of the slave address, the bus master sends a byte to the pca9545a, which is stored in the control register (see figure 2 ). if multiple bytes are received by the pca9545a, it saves the last byte received. this register can be written and read via the i 2 c bus. figure 2. control register one or several scn/sdn downstream pairs, or channels, are selected by the contents of the control register (see table 1 ). after the pca9545a has been addressed, the control register is written. the four lsbs of the control byte are used to determine which channel or channels are to be selected. when a channel is selected, the channel becomes active after a stop condition has been placed on the i 2 c bus. this ensures that all scn/sdn lines are in a high state when the channel is made active, so that no false conditions are generated at the time of connection. a stop condition must occur always right after the acknowledge cycle. 5 submit documentation feedback www .ti.com 1 1 1 0 a1 0 a0 slave address r/w fixed hardware selectable interrupt bits (read only) channel-selection bits (read/write) channel 0channel 1 channel 2 channel 3 int0 int1 int2 int3 int3 int2 int1 int0 b3 b2 b1 b0 7 6 5 4 3 2 1 0
interrupt handling pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 table 1. control register write (channel selection), control register read (channel status) (1) int3 int2 int1 int0 d3 b2 b1 b0 command 0 channel 0 disabled x x x x x x x 1 channel 0 enabled 0 channel 1 disabled x x x x x x x 1 channel 1 enabled 0 channel 2 disabled x x x x x x x 1 channel 2 enabled 0 channel 3 disabled x x x x x x x 1 channel 3 enabled no channel selected, 0 0 0 0 0 0 x 0 power-up/reset default state (1) several channels can be enabled at the same time. for example, b3 = 0, b2 = 1, b1 = 1, b0 = 0 means that channels 0 and 3 are disabled, and channels 1 are 2 and enabled. care should be taken not to exceed the maximum bus capacity. the pca9545a provides four interrupt inputs (one for each channel) and one open-drain interrupt output (see table 2 ). when an interrupt is generated by any device, it is detected by the pca9545a and the interrupt output is driven low. the channel does not need to be active for detection of the interrupt. a bit also is set in the control register. bits 4?7 of the control register correspond to channels 0?3 of the pca9545a, respectively. therefore, if an interrupt is generated by any device connected to channel 1, the state of the interrupt inputs is loaded into the control register when a read is accomplished. likewise, an interrupt on any device connected to channel 0 would cause bit 4 of the control register to be set on the read. the master then can address the pca9545a and read the contents of the control register to determine which channel contains the device generating the interrupt. the master then can reconfigure the pca9545a to select this channel and locate the device generating the interrupt and clear it. it should be noted that more than one device can provide an interrupt on a channel, so it is up to the master to ensure that all devices on a channel are interrogated for an interrupt. the interrupt inputs can be used as general-purpose inputs if the interrupt function is not required. if unused, interrupt input(s) must be connected to v cc . table 2. control register read (interrupt) (1) int3 int2 int1 int0 d3 b2 b1 b0 command 0 no interrupt on channel 0 x x x x x x x 1 interrupt on channel 0 0 no interrupt on channel 1 x x x x x x x 1 interrupt on channel 1 0 no interrupt on channel 2 x x x x x x x 1 interrupt on channel 2 0 no interrupt on channel 3 x x x x x x x 1 interrupt on channel 3 (1) several interrupts can be active at the same time. for example, int3 = 0, int2 = 1, int1 = 1, int0 = 0 means that there is no interrupt on channels 0 and 3, and there is interrupt on channels 1 and 2. 6 submit documentation feedback www .ti.com
reset input power-on reset voltage translation i 2 c interface pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 the reset input can be used to recover the pca9545a from a bus-fault condition. the registers and the i 2 c state machine within this device initialize to their default states if this signal is asserted low for a minimum of t wl . all channels also are deselected in this case. reset must be connected to v cc through a pullup resistor. when power is applied to v cc , an internal power-on reset holds the pca9545a in a reset condition until v cc has reached v por . at this point, the reset condition is released and the pca9545a registers and i 2 c state machine are initialized to their default states, all zeroes, causing all the channels to be deselected. thereafter, v cc must be lowered below 0.2 v to reset the device. the pass-gate transistors of the pca9545a are constructed such that the v cc voltage can be used to limit the maximum voltage that is passed from one i 2 c bus to another. figure 3 shows the voltage characteristics of the pass-gate transistors (note that the graph was generated using data specified in the electrical characteristics section of this data sheet). in order for the pca9545a to act as a voltage translator, the v pass voltage must be equal to or lower than the lowest bus voltage. for example, if the main bus is running at 5 v and the downstream buses are 3.3 v and 2.7 v, v pass must be equal to or below 2.7 v to effectively clamp the downstream bus voltages. as shown in figure 3 , v pass (max) is at 2.7 v when the pca9545a supply voltage is 3.5 v or lower, so the pca9545a supply voltage could be set to 3.3 v. pullup resistors then can be used to bring the bus voltages to their appropriate levels (see figure 13 ). figure 3. v pass voltage vs v cc the i 2 c bus is for two-way two-line communication between different ics or modules. the two lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. data transfer can be initiated only when the bus is not busy. one data bit is transferred during each clock pulse. the data on the sda line must remain stable during the high period of the clock pulse, as changes in the data line at this time are interpreted as control signals (see figure 4 ). 7 submit documentation feedback www .ti.com 2 maximum typical minimum v cc (v) 4.5 4 3.5 3 2.5 5 5.5 1 5 4.5 4 3.5 3 2.5 2 1.5 v pass (v)
pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 figure 4. bit transfer both data and clock lines remain high when the bus is not busy. a high-to-low transition of the data line while the clock is high is defined as the start condition (s). a low-to-high transition of the data line while the clock is high is defined as the stop condition (p) (see figure 5 ). figure 5. definition of start and stop conditions a device generating a message is a transmitter; a device receiving a message is the receiver. the device that controls the message is the master, and the devices that are controlled by the master are the slaves (see figure 6 ). figure 6. system configuration the number of data bytes transferred between the start and the stop conditions from transmitter to receiver is not limited. each byte of eight bits is followed by one acknowlege (ack) bit. the transmitter must release the sda line before the receiver can send an ack bit. when a slave receiver is addressed, it must generate an ack after the reception of each byte. also, a master must generate an ack after the reception of each byte that has been clocked out of the slave transmitter. the device that acknowledges must pull down the sda line during the ack clock pulse so that the sda line is stable low during the high pulse of the ack-related clock period (see figure 7 ). setup and hold times must be taken into account. 8 submit documentation feedback www .ti.com sda scl data line stable; data v alid change of data allowed sda scl start condition s stop condition p scl master transmitter/ receiver slave receiver slave transmitter/ receiver master transmitter master transmitter/ receiver i 2 c multiplexer slave sda
pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 figure 7. acknowledgment on the i 2 c bus a master receiver must signal an end of data to the transmitter by not generating an acknowledge (nack) after the last byte has been clocked out of the slave. this is done by the master receiver by holding the sda line high. in this event, the transmitter must release the data line to enable the master to generate a stop condition. data is transmitted to the pca9545a control register using the write mode shown in figure 8 . figure 8. write control register data is read from the pca9545a control register using the read mode shown in figure 9 . figure 9. read control register 9 submit documentation feedback www .ti.com a na s 1 1 1 0 0 a1 a0 1 sda int0 int3 int2 int1 p b3 b2 b1 b0 start condition r/w ack from slave nack from master stop condition slave address control register data output by t ransmitter scl from master start condition s 1 2 8 9 data output by receiver clock pulse for ack nack ack a a s 1 1 1 0 0 a1 a0 0 start condition sda r/w ack from slave ack from slave p b0 b1 b2 b3 x x x x stop condition slave address control register
absolute maximum ratings (1) recommended operating conditions (1) pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 over operating free-air temperature range (unless otherwise noted) min max unit v cc supply voltage range ?0.5 7 v v i input voltage range (2) ?0.5 7 v i i input current 20 ma i o output current 25 ma continuous current through v cc 100 ma continuous current through gnd 100 ma dgv package 92 dw package 58 gqn/zqn package 78 q ja package thermal impedance (3) c/w pw package 83 rgw package tbd rgy package 47 p tot total power dissipation 400 mw t stg storage temperature range ?65 150 c t a operating free-air temperature range ?40 85 c (1) stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. (3) the package thermal impedance is calculated in accordance with jesd 51-7. min max unit v cc supply voltage 2.3 5.5 v scl, sda 0.7 v cc 6 v ih high-level input voltage v a1, a0, int3? int0, reset 0.7 v cc v cc + 0.5 scl, sda ?0.5 0.3 v cc v il low-level input voltage v a1, a0, int3? int0, reset ?0.5 0.3 v cc t a operating free-air temperature ?40 85 c (1) all unused inputs of the device must be held at v cc or gnd to ensure proper device operation. refer to the ti application report, implications of slow or floating cmos inputs, literature number scba004. 10 submit documentation feedback www .ti.com
electrical characteristics pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 over recommended operating free-air temperature range (unless otherwise noted) parameter test conditions v cc min typ (1) max unit v por power-on reset voltage (2) no load, v i = v cc or gnd v por 1.6 2.1 v 5 v 3.6 4.5 v to 5.5 v 2.6 4.5 3.3 v 1.9 v pass switch output voltage v swin = v cc , i swout = ?100 m a v 3 v to 3.6 v 1.6 2.8 2.5 v 1.5 2.3 v to 2.7 v 1.1 2 i oh int v o = v cc 2.3 v to 5.5 v 10 m a v ol = 0.4 v 3 7 scl, sda i ol v ol = 0.6 v 2.3 v to 5.5 v 6 10 ma int v ol = 0.4 v 3 scl, sda 1 sc3?sc0, sd3?sd0 1 i i a1, a0 v i = v cc or gnd 2.3 v to 5.5 v 1 m a int3? int0 1 reset 1 5.5 v 3 12 operating mode f scl = 100 khz v i = v cc or gnd, i o = 0 3.6 v 3 11 2.7 v 3 10 5.5 v 0.3 1 i cc low inputs v i = gnd, i o = 0 3.6 v 0.1 1 m a 2.7 v 0.1 1 standby mode 5.5 v 0.3 1 high inputs v i = v cc , i o = 0 3.6 v 0.1 1 2.7 v 0.1 1 one int3? int0 input at 0.6 v, 8 15 other inputs at v cc or gnd int3? int0 one int3? int0 input at v cc ? 0.6 v, 8 15 other inputs at v cc or gnd supply-current d i cc 2.3 v to 5.5 v m a change scl or sda input at 0.6 v, 8 15 other inputs at v cc or gnd scl, sda scl or sda input at v cc ? 0.6 v, 8 15 other inputs at v cc or gnd a1, a0 4.5 6 c i int3? int0 v i = v cc or gnd 2.3 v to 5.5 v 4.5 6 pf reset 4.5 5.5 scl, sda 15 19 c io(off) (3) v i = v cc or gnd, switch off 2.3 v to 5.5 v pf sc3?sc0, sd3?sd0 6 8 4.5 v to 5.5 v 4 9 16 v o = 0.4 v, i o = 15 ma r on switch on-state resistance 3 v to 3.6 v 5 11 20 w v o = 0.4 v, i o = 10 ma 2.3 v to 2.7 v 7 16 45 (1) all typical values are at nominal supply voltage (2.5-v, 3.3-v, or 5-v v cc ), t a = 25 c. (2) the power-on reset circuit resets the i 2 c bus logic with v cc < v por . v cc must be lowered to 0.2 v to reset the device. (3) c io(on) depends on the device capacitance and load that is downstream from the device. 11 submit documentation feedback www .ti.com
i 2 c interface timing requirements switching characteristics pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 over recommended operating free-air temperature range (unless otherwise noted) (see figure 10 ) standard mode fast mode i 2 c bus i 2 c bus unit min max min max f scl i 2 c clock frequency 0 100 0 400 khz t sch i 2 c clock high time 4 0.6 m s t scl i 2 c clock low time 4.7 1.3 m s t sp i 2 c spike time 50 50 ns t sds i 2 c serial-data setup time 250 100 ns t sdh i 2 c serial-data hold time 0 (1) 0 (1) m s t icr i 2 c input rise time 1000 20 + 0.1c b (2) 300 ns t icf i 2 c input fall time 300 20 + 0.1c b (2) 300 ns t ocf i 2 c output fall time 10-pf to 400-pf bus 300 20 + 0.1c b (2) 300 ns t buf i 2 c bus free time between stop and start 4.7 1.3 m s t sts i 2 c start or repeated start condition setup 4.7 0.6 m s t sth i 2 c start or repeated start condition hold 4 0.6 m s t sps i 2 c stop condition setup 4 0.6 m s scl low to sda output low t vdl(data) valid-data time (high to low) (3) 1 1 m s valid scl low to sda output high t vdh(data) valid-data time (low to high) (3) 0.6 0.6 m s valid ack signal from scl low t vd(ack) valid-data time of ack condition 1 1 m s to sda output low c b i 2 c bus capacitive load 400 400 pf (1) a device internally must provide a hold time of at least 300 ns for the sda signal (referred to as the v ih min of the scl signal), in order to bridge the undefined region of the falling edge of scl. (2) c b = total bus capacitance of one bus line in pf (3) data taken using a 1-k w pullup resistor and 50-pf load (see figure 10 ) over recommended operating free-air temperature range, c l 100 pf (unless otherwise noted) (see figure 12 ) from to parameter min max unit (input) (output) r on = 20 w , c l = 15 pf 0.3 t pd (1) propagation delay time sda or scl sdn or scn ns r on = 20 w , c l = 50 pf 1 t iv interrupt valid time (2) intn int 4 m s t ir interrupt reset delay time (2) intn int 2 m s (1) the propagation delay is the calculated rc time constant of the typical on-state resistance of the switch and the specified load capacitance, when driven by an ideal voltage source (zero output impedance). (2) data taken using a 4.7-k w pullup resistor and 100-pf load (see figure 12 ) 12 submit documentation feedback www .ti.com
interrupt and reset timing requirements pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 over recommended operating free-air temperature range (unless otherwise noted) (see figure 12 ) parameter min max unit t pwrl low-level pulse duration rejection of intn inputs 1 m s t pwrh high-level pulse duration rejection of intn inputs 0.5 m s t wl pulse duration, reset low 6 ns t rst (1) reset time (sda clear) 500 ns t rec(sta) recovery time from reset to start 0 ns (1) t rst is the propagation delay measured from the time the reset pin is first asserted low to the time the sda pin is asserted high, signaling a stop condition. it must be a minimum of t wl . 13 submit documentation feedback www .ti.com
parameter measurement information pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r /t f = 30 ns. c. the outputs are measured one at a time, with one transition per measurement. figure 10. i 2 c interface load circuit, byte descriptions, and voltage waveforms 14 submit documentation feedback www .ti.com r l = 1 k w v cc c l = 50 pf (see note a) t buf t icr t sth t sds t sdh t icf t icr t scl t sch t sts t vd(ack) or t vdl t vdh 0.3 v cc stop condition t sps repeat start condition start or repeatstart condition scl sda start condition (s) address bit 7 (msb) databit 0 (lsb) stop condition (p) t wo bytes for complete device programming i 2 c port load configura tion volt age w aveforms t icf stop condition (p) t sp dut sdn, scn 0.7 v cc 0.3 v cc 0.7 v cc r/w bit 0 (lsb) ack (a) data bit 7 (msb) address bit 1 address bit 6 ack (a) byte description i 2 c address + r/w control register data 12
pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 parameter measurement information (continued) figure 11. reset timing a. c l includes probe and jig capacitance. b. all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 w , t r /t f = 30 ns. figure 12. interrupt load circuit and voltage waveforms 15 submit documentation feedback www .ti.com scl sda ledx reset 30% 50% 50% led off start ack or read cycle t rst t wl t rec t rst r l = 4.7 k v cc c l = 100 pf (see note a) interrupt load configura tion dut int 0.5 v cc intn (input) volt age w a veforms (t iv ) t iv volt age w a veforms (t ir ) int (output) 0.5 v cc intn (input) int (output) 0.5 v cc 0.5 v cc t ir
application information pca9545a 4-channel i 2 c and smbus switch with interrupt logic and reset functions scps147c ? october 2005 ? revised october 2006 figure 13 shows an application in which the pca9545a can be used. a. if the device generating the interrupt has an open-drain output structure or can be 3-stated, a pullup resistor is required. if the device generating the interrupt has a totem-pole output structure and cannot be 3-stated, a pullup resistor is not required. the interrupt inputs should not be left floating. b. pin numbers shown are for dgv, dw, pw, and rgy packages. figure 13. typical application 16 submit documentation feedback www .ti.com pca9545a sd1 sda scl sda channel 0 channel 1 channel 2 channel 3 see note a i 2 c/smbus master scl int reset int1 sc1 sd2sc2 sd3 sc3 int2 int3 sd0 int0 sc0 v cc = 2.7 v to 5.5 v v cc = 3.3 v v cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v v cc = 2.7 v to 5.5 v see note a see note a see note a 1918 17 3 20 56 4 8 9 7 12 13 11 15 16 14 21 10 a1a0 gnd
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) pca9545adgvr active tvsop dgv 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545adgvt preview tvsop dgv 20 250 tbd call ti call ti pca9545adw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545adwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545adwt preview soic dw 20 250 tbd call ti call ti pca9545agqnr nrnd bga mi crosta r juni or gqn 20 1000 tbd snpb level-1-240c-unlim pca9545apw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545apwe4 active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545apwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545apwre4 active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545apwt active tssop pw 20 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim PCA9545APWTE4 active tssop pw 20 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim pca9545argwr preview qfn rgw 20 3000 tbd call ti call ti pca9545argyr active qfn rgy 20 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1year pca9545argyrg4 active qfn rgy 20 1000 green (rohs & no sb/br) cu nipdau level-2-260c-1year pca9545azqnr active bga mi crosta r juni or zqn 20 1000 green (rohs & no sb/br) snagcu level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) package option addendum www.ti.com 30-mar-2007 addendum-page 1
(3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 30-mar-2007 addendum-page 2

mechanical data mpds006c february 1996 revised august 2000 post office box 655303 ? dallas, texas 75265 dgv (r-pdso-g**) plastic small-outline 24 pins shown 14 3,70 3,50 4,90 5,10 20 dim pins ** 4073251/e 08/00 1,20 max seating plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 112 24 13 4,30 4,50 0,16 nom gage plane a 7,90 7,70 38 24 16 4,90 5,10 3,70 3,50 a max a min 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 m 0,07 0,40 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. d. falls within jedec: 24/48 pins mo-153 14/16/20/56 pins mo-194

mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. cu stomers should obtain the latest relevant information before placing orders and should verify that such info rmation is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and othe r quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by governm ent requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti component s. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implie d, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are us ed. information published by ti regarding third-party products or services does not consti tute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the pat ents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, lim itations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements diffe rent from or beyond the parameters stated by ti for that product or service voids all express and any imp lied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.c om audio www.ti.com/audio data converters dataconverter.ti.co m automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security low power wireless www.ti.com/lpw telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 6553 03 dallas, texas 75265 copyright ? 2007, texas instruments incorporated

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